1. Field of the Invention
This invention relates to an arithmetic logic unit (ALU), especially one forming part of a graphics processor.
2. Description of the Related Art
The central functions of a computer require arithmetic and logical operations to be performed upon data stored in its memory. An arithmetic logic unit forms the basis of such operations. Data is supplied to the ALU, an arithmetic or logical operation performed, and the resulting data set transferred from the unit and utilized elsewhere within the computer system.
Binary adders are well known in the art and perform the core function of the ALU. A binary adder consists of a chain (the carry chain) of connected bit stages (adders). With the exception of the least significant stage at the start of the chain (which is usually a half as opposed to a full adder), they receive three inputs: the two bits to be added and the carry from the previous stage. Two outputs are generated: a sum and a carry, which is output to the next stage. In turn this produces a carry out of the following stages and so on as it ripples through the binary adder.
Within the prior art, efforts have concentrated on increasing the ALU processing speed by accelerating the carry chain propagation. FR-A-2570851 describes a system in which an ALU is divided into two groups of cells of high- and low-order bits, respectively. The calculation and the carry for the lower-order bits follow conventional practice as described above, whereas for the higher-order group there are two chains working in parallel for the calculation and propagation of the carry. One of these high-order chains receives an initial input of 1 and the other 0; each one then computes a result for the high-order part of the chain. A multiplexer receives the true value of the carry from the lower-order bit computation and selects the correct high-order computation.
This prior art allows only the fixed division of the carry chain and ultimately, in the worst case, utilizes the complete length of the chain to perform one operation. Often it would be desirable to divide the carry chain into independent lengths, allowing the ALU to perform individual and separate operations. In a conventional ALU, this can only be achieved by several separate passes through the carry chain, with associated shifting and masking computation being necessary.
It is often desirable, for example in graphics processors, to be able to perform operations on variable-length data, for example 1, 2, 4 or 8 bits representing a picture element (pixel). An object of the invention is to provide an arithmetic logic unit which has general application but has particular advantages for use in a graphics processor in which simultaneous operations can be performed on variably sized bit fields.